22 lines
376 B
Verilog
22 lines
376 B
Verilog
// pr1750870
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module test (FUSE_Q);
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parameter fuse_a_msb = 4;
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parameter fuse_q_msb = (2**(fuse_a_msb+1))-1;
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input [fuse_q_msb:0] FUSE_Q;
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initial begin
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$display("fuse_q_msb = %d", fuse_q_msb);
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if ($bits(FUSE_Q) != 32) begin
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$display("FAILED -- $bits(FUSE_Q) = %d", $bits(FUSE_Q));
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$finish;
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end
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$display("PASSED");
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end
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endmodule
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