53 lines
1.5 KiB
Verilog
53 lines
1.5 KiB
Verilog
module array_assign();
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parameter MSB = 1;
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integer ii;
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reg signed [2:0] ar_reg[0:MSB];
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wire signed [4:0] as_wr;
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// compiled with "-g2 -g2x"
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// FAILED at this line
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assign as_wr = {{2{ar_reg[0][2]}},ar_reg[1]};
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always @(as_wr)
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for(ii=0; ii<(MSB+1); ii=ii+1)
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begin
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$display(" %t ar_reg=%0d w_assign=%0d", $time, ar_reg[ii], as_wr);
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$display(" %t ar_reg[0]=3'b%3b ar_reg[1]=3'b%3b", $time, ar_reg[0], ar_reg[1]);
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$display(" %t as_wr=5'b%5b", $time, as_wr);
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end
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initial
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begin
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$display("\n*** module %m **************************************");
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#10;
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for(ii=0; ii<(MSB+1); ii=ii+1)
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ar_reg[ii] <= 3'sd1;
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#10;
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for(ii=0; ii<(MSB+1); ii=ii+1)
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ar_reg[ii] <= 3'sd0;
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$display("\n\n");
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end
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endmodule
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/* expected output - START
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module array_assign
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10 ar_reg=1 w_assign=1
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10 ar_reg[0]=3'b001 ar_reg[1]=3'b001
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10 as_wr=5'b00001
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10 ar_reg=1 w_assign=1
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10 ar_reg[0]=3'b001 ar_reg[1]=3'b001
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10 as_wr=5'b00001
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20 ar_reg=0 w_assign=0
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20 ar_reg[0]=3'b000 ar_reg[1]=3'b000
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20 as_wr=5'b00000
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20 ar_reg=0 w_assign=0
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20 ar_reg[0]=3'b000 ar_reg[1]=3'b000
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20 as_wr=5'b00000
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expected output - END */
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