134 lines
3.6 KiB
Verilog
134 lines
3.6 KiB
Verilog
module sysSimpleTest();
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reg CLK;
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reg RST_N;
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initial begin
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#0
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RST_N = 1'b0;
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#1;
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CLK = 1'b1;
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$display("reset");
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#1;
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RST_N = 1'b1;
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$display("reset done");
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end
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always
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begin
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#5;
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CLK = 1'b0 ;
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#5;
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CLK = 1'b1 ;
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end
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// register y
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reg [98 : 0] y;
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wire [98 : 0] y$D_IN;
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wire y$EN;
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// register z
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reg [98 : 0] z;
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wire [98 : 0] z$D_IN;
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wire z$EN;
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// remaining internal signals
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wire [98 : 0] IF_y_SLT_0_AND_NOT_z_SLT_0_OR_NOT_y_SLT_0_AND__ETC___d29,
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IF_y_SLT_0_THEN_NEG_IF_y_SLT_0_THEN_NEG_y_0_EL_ETC___d28,
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IF_y_SLT_0_THEN_NEG_y_0_ELSE_y_1_QUOT_IF_z_SLT_ETC___d30,
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IF_y_SLT_0_THEN_NEG_y_0_ELSE_y_1_REM_IF_z_SLT__ETC___d31,
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x__h201,
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y__h141,
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z_MUL_IF_y_SLT_0_AND_NOT_z_SLT_0_OR_NOT_y_SLT__ETC___d17;
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wire y_SLT_0___d33,
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z_MUL_IF_y_SLT_0_AND_NOT_z_SLT_0_OR_NOT_y_SLT__ETC___d22,
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z_SLT_0___d32;
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// register y
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assign y$D_IN = 99'h0 ;
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assign y$EN = 1'b0 ;
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// register z
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assign z$EN = 1'b0 ;
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assign z$D_IN = 99'h0 ;
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// remaining internal signals
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assign IF_y_SLT_0_AND_NOT_z_SLT_0_OR_NOT_y_SLT_0_AND__ETC___d29 =
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(y_SLT_0___d33 && !z_SLT_0___d32 ||
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!y_SLT_0___d33 && z_SLT_0___d32) ?
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-IF_y_SLT_0_THEN_NEG_y_0_ELSE_y_1_QUOT_IF_z_SLT_ETC___d30 :
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IF_y_SLT_0_THEN_NEG_y_0_ELSE_y_1_QUOT_IF_z_SLT_ETC___d30 ;
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assign IF_y_SLT_0_THEN_NEG_IF_y_SLT_0_THEN_NEG_y_0_EL_ETC___d28 =
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y_SLT_0___d33 ?
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-IF_y_SLT_0_THEN_NEG_y_0_ELSE_y_1_REM_IF_z_SLT__ETC___d31 :
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IF_y_SLT_0_THEN_NEG_y_0_ELSE_y_1_REM_IF_z_SLT__ETC___d31 ;
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assign IF_y_SLT_0_THEN_NEG_y_0_ELSE_y_1_QUOT_IF_z_SLT_ETC___d30 =
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x__h201 / y__h141 ;
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assign IF_y_SLT_0_THEN_NEG_y_0_ELSE_y_1_REM_IF_z_SLT__ETC___d31 =
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x__h201 % y__h141 ;
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assign x__h201 = y_SLT_0___d33 ? -y : y ;
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assign y_SLT_0___d33 =
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(y ^ 99'h4000000000000000000000000) <
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99'h4000000000000000000000000 ;
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assign y__h141 = z_SLT_0___d32 ? -z : z ;
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assign z_MUL_IF_y_SLT_0_AND_NOT_z_SLT_0_OR_NOT_y_SLT__ETC___d17 =
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z * IF_y_SLT_0_AND_NOT_z_SLT_0_OR_NOT_y_SLT_0_AND__ETC___d29 ;
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assign z_MUL_IF_y_SLT_0_AND_NOT_z_SLT_0_OR_NOT_y_SLT__ETC___d22 =
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z_MUL_IF_y_SLT_0_AND_NOT_z_SLT_0_OR_NOT_y_SLT__ETC___d17 +
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IF_y_SLT_0_THEN_NEG_IF_y_SLT_0_THEN_NEG_y_0_EL_ETC___d28 ==
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y ;
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assign z_SLT_0___d32 =
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(z ^ 99'h4000000000000000000000000) <
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99'h4000000000000000000000000 ;
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// handling of inlined registers
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always@(posedge CLK)
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begin
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if (!RST_N)
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begin
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// y <= 1;
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// z <= 1;
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y <= 99'h7FFFFFF04A62A1453402211B2;
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z <= 99'h000000023E84321AAFCCC70C2;
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end
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else
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begin
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if (y$EN) y <= y$D_IN;
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if (z$EN) z <= z$D_IN;
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end
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end
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// synopsys translate_off
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initial
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begin
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y = 99'h2AAAAAAAAAAAAAAAAAAAAAAAA;
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z = 99'h2AAAAAAAAAAAAAAAAAAAAAAAA;
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end
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// synopsys translate_on
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// handling of system tasks
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// synopsys translate_off
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always@(negedge CLK)
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begin
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#0;
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if (RST_N)
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if (z_MUL_IF_y_SLT_0_AND_NOT_z_SLT_0_OR_NOT_y_SLT__ETC___d22)
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$display("OK: %0d * %0d + %0d == %0d",
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$signed(z),
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$signed(IF_y_SLT_0_AND_NOT_z_SLT_0_OR_NOT_y_SLT_0_AND__ETC___d29),
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$signed(IF_y_SLT_0_THEN_NEG_IF_y_SLT_0_THEN_NEG_y_0_EL_ETC___d28),
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$signed(y));
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if (RST_N)
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if (!z_MUL_IF_y_SLT_0_AND_NOT_z_SLT_0_OR_NOT_y_SLT__ETC___d22)
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$display("BAD: %0d * %0d + %0d != %0d",
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$signed(z),
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$signed(IF_y_SLT_0_AND_NOT_z_SLT_0_OR_NOT_y_SLT_0_AND__ETC___d29),
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$signed(IF_y_SLT_0_THEN_NEG_IF_y_SLT_0_THEN_NEG_y_0_EL_ETC___d28),
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$signed(y));
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if (RST_N) $finish(32'd0);
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end
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// synopsys translate_on
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endmodule // sysSimpleTest
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