79 lines
1.5 KiB
Verilog
79 lines
1.5 KiB
Verilog
/*
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* This program is explicitly placed in the public domain for any uses
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* whatsoever.
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*/
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module TestMultiplier();
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reg clk;
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initial begin
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clk = 0;
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forever #0.5 clk = ~clk;
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end
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reg[5:0] left, right;
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wire[2:0] exp;
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Multiplier mul(clk, left, right, exp);
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parameter ONE = {3'b011, 3'b0}; // 1.000 * 2**(3 - bias of 3) == 1.000
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always @ (posedge clk) begin
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left = ONE;
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right = ONE;
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#10
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if (exp !== 3'b011)
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$display("FAIL: expected %b, got %b",
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3'b011, exp);
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else
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$display("PASSED");
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$finish();
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end
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endmodule
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/**
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* A little bit of an incomplete floating-point multiplier. In/out format is
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* [5:3] specify biased exponent (and hidden bit), [2:0] specify fraction.
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*
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* @param left[5:0], right[5:0]
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* values being multiplied
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* @param exp[2:0]
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* exponent from product of left and right when put in the floating-point
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* format of left/right
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*/
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module Multiplier(clk,
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left, right,
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exp);
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input clk;
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input[5:0] left, right;
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output[2:0] exp;
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reg[2:0] exp;
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// IMPLEMENTATION
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wire signed[2:0] expl = left[5:3] - 3;
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wire signed[2:0] expr = right[5:3] - 3;
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/** Sum of unbiased exponents in operands. */
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reg signed[3:0] sumExp;
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always @ (posedge clk) begin
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sumExp <= (expl + expr) < -2 // why can't I move -2 to the right-hand side?
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? -3
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: expl + expr;
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exp[2:0] <= sumExp + 3;
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end
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endmodule
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