54 lines
949 B
Verilog
54 lines
949 B
Verilog
`timescale 1ns/1ps
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module fail ();
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reg pz;
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reg [4:0] p;
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wire em, net0102;
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initial begin
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p = 0;
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pz = 0;
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$monitor("time=%0t", $time,": em=", em, ", pz=", pz, ", p=%b", p);
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while (p < 5'b11111)
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#10 p = p+1;
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#1; // avoid final race
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$finish(0);
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end
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nr1 I1 (em, net0102, pz, p[0]);
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nr2 I2 (net0102, p[1], p[2], p[3], p[4]);
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endmodule
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module nr1 (zn, a1, a2, a3);
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output zn;
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input a1, a2, a3;
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not G1(N1, a1);
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not G2(zn, N2);
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or G3(N2, N1, a2, a3);
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specify
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(a1 +=> zn) = (0.500, 0.500);
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(a2 -=> zn) = (0.500, 0.500);
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(a3 -=> zn) = (0.500, 0.500);
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endspecify
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endmodule
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module nr2 (zn, a1, a2, a3, a4);
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output zn;
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input a1, a2, a3, a4;
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or G1(N1, a1, a2, a3, a4);
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not G2(zn, N1);
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specify
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(a1 -=> zn) = (0.500, 0.500);
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(a2 -=> zn) = (0.500, 0.500);
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(a3 -=> zn) = (0.500, 0.500);
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(a4 -=> zn) = (0.500, 0.500);
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endspecify
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endmodule
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