41 lines
784 B
Verilog
41 lines
784 B
Verilog
module bittest;
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reg signed [5:0] m;
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reg signed [7:0] n;
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reg signed [18:0] p;
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reg signed [8:0] s;
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reg b;
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reg signed c;
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reg d;
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always @(m, n, c) begin
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p <= m * n; // m and n are signed, so do signed multiply
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s <= m + b; // b is UNsigned, so do unsigned pad and add.
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d <= c == 1; // c and the literal 1 are signed, so do signed compare.
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end
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initial begin
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#10;
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m <= -25;
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n <= 29;
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b <= 1;
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c <= 1;
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#10;
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$display("p=%d s=%d d=%d", p, s, d);
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if (s !== 9'd40) begin
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$display("FAILED -- s='b%b", s);
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$finish;
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end
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if (p !== -19'd725) begin
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$display("FAILED == p='b%b", p);
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$finish;
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end
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if (d !== 0) begin
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$display("FAILED == d='b%b", d);
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$finish;
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end
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$display("PASSED");
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end
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endmodule
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