40 lines
781 B
Verilog
40 lines
781 B
Verilog
`define REG_DELAY 1
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module ansireg(input clk, reset, input [7:0] d, output reg [7:0] q );
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always @(posedge clk or posedge reset)
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if(reset)
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q <= #(`REG_DELAY) 8'h00;
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else
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q <= #(`REG_DELAY) d;
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endmodule
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module main;
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reg clk, reset;
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reg [7:0] d;
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wire [7:0] q;
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ansireg U(clk, reset, d, q);
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initial begin
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clk = 0;
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reset = 0;
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d = 'hff;
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#(2*`REG_DELAY) clk <= 1;
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#(2*`REG_DELAY) if (q !== d) begin
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$display("FAILED -- clk=%b, reset=%b, d=%b, q=%b", clk, reset, d, q);
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$finish;
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end
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reset <= 1;
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#(1 + `REG_DELAY) if (q !== 8'h00) begin
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$display("FAILED -- clk=%b, reset=%b, d=%b, q=%b", clk, reset, d, q);
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$finish;
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end
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$display("PASSED");
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end // initial begin
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endmodule // main
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