85 lines
2.4 KiB
Verilog
85 lines
2.4 KiB
Verilog
module top;
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reg pass = 1'b1;
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integer count;
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reg [2:0] icount;
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reg clk = 0;
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reg [3:0] in = 4'h0;
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reg [7:0] result;
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always #10 clk = ~clk;
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always #20 in = in + 4'h1;
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initial begin
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count = 3;
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result[3:0] <= repeat(count) @(posedge clk) in;
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if ($simtime != 0 || result !== 8'bx) begin
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$display("Failed repeat(3) blocked at %0t, expected 8'hxx, got %h",
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$simtime, result);
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pass = 1'b0;
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end
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@(result);
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if ($simtime != 50 || result !== 8'hx0) begin
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$display("Failed repeat(3) at %0t, expected 8'hx0, got %h",
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$simtime, result);
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pass = 1'b0;
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end
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#15;
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count = 0;
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result[7:4] <= repeat(count) @(posedge clk) in;
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@(result); // Reals happen faster so they can use an #0, vectors are slower.
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if ($simtime != 65 || result !== 8'h30) begin
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$display("Failed repeat(0) at %0t, expected 8'h30, got %h",
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$simtime, result);
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pass = 1'b0;
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end
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#20;
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count = -1;
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result[8:5] <= repeat(count) @(posedge clk) in;
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@(result); // Reals happen faster so they can use an #0, vectors are slower.
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if ($simtime != 85 || result !== 8'h90) begin
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$display("Failed repeat(-1) at %0t, expected 8'h80, got %h",
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$simtime, result);
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pass = 1'b0;
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end
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#20;
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result[7:4] <= @(posedge clk) 4'h0;
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result[7:4] <= @(posedge clk) in; // This one sets the final value.
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@(result);
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if ($simtime != 110 || result !== 8'h50) begin
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$display("Failed @ at %0t, expected 8'h50, got %h",
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$simtime, result);
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pass = 1'b0;
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end
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icount = 3'd2;
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result[3:0] <= @(posedge clk) 4'h1;
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result[7:4] <= repeat(icount) @(posedge clk) 4'h2;
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result[1:-2] <= repeat(3) @(posedge clk) 4'h3;
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@(result);
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if ($simtime != 130 || result !== 8'h51) begin
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$display("Failed first @ at %0t, expected 8'h51, got %h",
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$simtime, result);
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pass = 1'b0;
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end
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@(result);
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if ($simtime != 150 || result !== 8'h21) begin
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$display("Failed second @ at %0t, expected 8'h21, got %h",
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$simtime, result);
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pass = 1'b0;
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end
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@(result);
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if ($simtime != 170 || result !== 8'h20) begin
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$display("Failed third @ at %0t, expected 8'h20, got %h",
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$simtime, result);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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$finish;
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end
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endmodule
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