75 lines
1.7 KiB
Verilog
75 lines
1.7 KiB
Verilog
//
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// Copyright (c) 1999 Steven Wilson (stevew@home.com)
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//
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// This source code is free software; you can redistribute it
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// and/or modify it in source code form under the terms of the GNU
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// General Public License as published by the Free Software
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// Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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//
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// SDW - Validate various module formats
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// Template 1
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module mod1 ;
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endmodule
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// Template 2
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module mod2 ();
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endmodule
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// Template 3
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module mod3 (a,b);
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input a;
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input b;
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endmodule
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//Template 4 -
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module mod4 (ident1,out1);
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input [31:0] ident1;
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output [31:0] out1;
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wire [31:0] out1 = ident1;
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endmodule
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module main ();
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wire [31:0] out1,out2;
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reg [31:0] val1,val2;
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reg error;
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mod4 inst1 (val1,out1); // Ordered port list
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mod4 inst2 (.ident1(val2),.out1(out2)); // List by portname
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initial
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begin
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error = 0;
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val1 = 32'h11223344;
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#1 if(out1 != 32'h11223344)
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begin
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$display("FAILED - module 3.12A - Ordered module port list failed");
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error = 1;
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end
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val2 = 32'h44332211;
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#1 if(out2 != 32'h44332211)
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begin
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$display("FAILED -module 3.12A -named module port list (.x(a)) failed");
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error = 1;
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end
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if(error == 0)
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$display("PASSED");
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end
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endmodule // main
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