72 lines
1.8 KiB
Verilog
72 lines
1.8 KiB
Verilog
//
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// Copyright (c) 1999 Steven Wilson (stevew@home.com)
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//
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// This source code is free software; you can redistribute it
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// and/or modify it in source code form under the terms of the GNU
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// General Public License as published by the Free Software
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// Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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//
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// SDW - Validate fork template 1
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module main ;
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reg [3:0] value1,value2 ;
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reg [3:0] ret1,ret2 ;
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reg error;
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always @(value1 or value2)
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begin
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fork
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#10 ret1 = value1;
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#22 ret2 = value2;
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join
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end
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initial
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begin
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error = 0;
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#1 ;
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value1 = 1;
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value2 = 2;
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ret1 = 0;
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ret2 = 0;
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#12;
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if(ret1 !== 1)
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begin
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$display("FAILED - force3.19A first statement didn't execute(1)");
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error = 1;
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end
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if(ret2 !== 0)
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begin
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$display("FAILED - force3.19A second stmt executed? is %d sb %d",
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1'b0,ret2);
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error = 1;
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end
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#10;
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if(ret1 !== 1)
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begin
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$display("FAILED -fork3.19A First statement problem sb 1, is %d",ret1);
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error = 1;
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end
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if(ret2 !== 2)
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begin
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$display("FAILED -fork3.19A First statement problem sb 2, is %d",ret1);
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error = 1;
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end
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if(error == 0)
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$display("PASSED");
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end
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endmodule
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