25 lines
540 B
Verilog
25 lines
540 B
Verilog
module top;
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reg pass;
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reg [3:0] value;
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reg [3:0] in;
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initial begin
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pass = 1'b1;
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value = 4'b1001;
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if (value !== 4'b1001) begin
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$display("Failed: initial value, expected 4'b1001, got %b", value);
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pass = 1'b0;
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end
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in = 4'bzx10;
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// This should work since it is really the whole value.
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force value[0 +: 4] = in;
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if (value !== 4'bzx10) begin
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$display("Failed: force value, expected 4'bzx10, got %b", value);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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