37 lines
456 B
Verilog
37 lines
456 B
Verilog
module part3 (
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\6A_A ,
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\6Y_A ,
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VCC ,
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GND ,
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\6A_B ,
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\6Y_B ,
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\6A_C ,
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\6Y_C ,
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\6A_D ,
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\6Y_D ,
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\6A_E ,
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// note: with space before the nl below
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\6Y_E
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) ;
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input \6A_A ;
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output \6Y_A ;
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input VCC ;
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input GND ;
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input \6A_B ;
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output \6Y_B ;
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input \6A_C ;
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output \6Y_C ;
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input \6A_D ;
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output \6Y_D ;
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input \6A_E ;
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output \6Y_E ;
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assign \6Y_A = ~\6A_A ;
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assign \6Y_B = ~\6A_B ;
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assign \6Y_C = ~\6A_C ;
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assign \6Y_D = ~\6A_D ;
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assign \6Y_E = ~\6A_E ;
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endmodule
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