60 lines
1.0 KiB
Verilog
60 lines
1.0 KiB
Verilog
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module DFF
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(output reg Q0,
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output reg [1:0] Q1,
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input wire D0,
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input wire [1:0] D1,
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input wire CLK,
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input wire RST
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/* */);
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always @(posedge CLK or posedge RST)
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if (RST) begin
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Q0 <= 0;
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Q1 <= 0;
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end else begin
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Q0 <= D0;
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Q1 <= D1;
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end
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endmodule // dut
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module main;
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wire q0;
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wire [1:0] q1;
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reg d0, clk, rst;
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reg [1:0] d1;
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DFF dut (.Q0(q0), .Q1(q1), .D0(d0), .D1(d1), .CLK(clk), .RST(rst));
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initial begin
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clk <= 1;
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d0 <= 0;
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d1 <= 2;
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#1 rst <= 1;
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#1 if (q0 !== 1'b0 || q1 !== 1'b0) begin
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$display("FAILED -- RST=%b, Q0=%b, Q1=%b", rst, q0, q1);
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$finish;
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end
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#1 rst <= 0;
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#1 if (q0 !== 1'b0 || q1 !== 1'b0) begin
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$display("FAILED -- RST=%b, Q0=%b, Q1=%b", rst, q0, q1);
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$finish;
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end
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#1 clk <= 0;
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#1 clk <= 1;
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#1 if (q0 !== d0 || q1 !== d1) begin
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$display("FAILED -- Q0=%b Q1=%b, D0=%b D1=%b", q0, q1, d0, d1);
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$finish;
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end
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$display("PASSED");
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$finish;
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end
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endmodule // main
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