56 lines
819 B
Verilog
56 lines
819 B
Verilog
module top();
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reg CLK;
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reg RST;
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reg [3:1] D;
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reg EN;
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reg [3:1] Q;
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always @(posedge CLK or posedge RST) begin
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if (RST) begin
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Q[1] <= 1'b0;
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Q[2] <= 1'b1;
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Q[3] <= 1'b0;
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end
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else if (EN) begin
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Q[1] <= D[1];
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Q[2] <= ~D[2];
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Q[3] <= D[3];
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end
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end
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reg failed;
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(* ivl_synthesis_off *)
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initial begin
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failed = 0;
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$monitor("%b %b %b %b", CLK, EN, D, Q);
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CLK = 0;
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RST = 1;
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EN = 0;
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D = 3'b111;
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#1 CLK = 1;
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#1 CLK = 0;
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if (Q !== 3'b010) failed = 1;
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EN = 1;
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#1 CLK = 1;
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#1 CLK = 0;
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if (Q !== 3'b010) failed = 1;
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RST = 0;
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EN = 0;
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#1 CLK = 1;
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#1 CLK = 0;
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if (Q !== 3'b010) failed = 1;
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EN = 1;
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#1 CLK = 1;
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#1 CLK = 0;
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if (Q !== 3'b101) failed = 1;
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#1;
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if (failed)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule
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