59 lines
1.7 KiB
Verilog
59 lines
1.7 KiB
Verilog
//
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// Copyright (c) 2001 Steve Williams <steve@icarus.com>
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//
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// This source code is free software; you can redistribute it
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// and/or modify it in source code form under the terms of the GNU
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// General Public License as published by the Free Software
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// Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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//
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/*
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* The $depost system task takes the inputs a depositible object and a
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* value to deposit. The $deposit works like a blocking assignment, so
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* the target takes the value right away.
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*
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* This example tests the $deposit on a wire object. What that means is
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* that the wire takes on the deposited value, but that value doesn't
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* stick if its normal input changes.
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*/
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module main ;
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reg in;
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wire test = in;
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initial begin
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in = 1'b0;
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#1 if (test !== 1'b0) begin
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$display("FAILED -- test starts out as %b", test);
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//$finish;
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end
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$deposit(test, 1'b1);
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#1 if (test !== 1'b1) begin
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$display("FAILED -- test after deposit is %b", test);
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$finish;
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end
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in = 1'bz;
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#1 if (test !== 1'bz) begin
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$display("FAILED -- test after input is %b", test);
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$finish;
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end
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$display("PASSED");
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end
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endmodule
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