38 lines
707 B
Verilog
38 lines
707 B
Verilog
module top;
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reg pass = 1'b1;
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reg [7:0] in;
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wire real out = in;
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initial begin
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// $monitor(in,, out);
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#1;
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if (out != 0.0) begin
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$display("Failed: initial value, expected 0.0, got %g", out);
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pass = 1'b0;
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end
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in = 0;
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#1;
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if (out != 0.0) begin
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$display("Failed: 0 value, expected 0.0, got %g", out);
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pass = 1'b0;
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end
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in = 1;
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#1;
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if (out != 1.0) begin
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$display("Failed: 1 value, expected 1.0, got %g", out);
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pass = 1'b0;
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end
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in = -1;
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#1;
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if (out != 255.0) begin
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$display("Failed: -1 value, expected -255.0, got %g", out);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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