100 lines
2.3 KiB
Verilog
100 lines
2.3 KiB
Verilog
module top;
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reg pass = 1'b1;
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real in, bin;
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wire [7:0] out = in;
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wire signed [34:0] big = bin;
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initial begin
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// $monitor(in,, out,, bin,, big);
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bin = 8589934592.5; // 2**33+0.5 overflows a 32 bit long.
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#1;
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if (big !== 35'sd8589934593) begin
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$display("Failed: multiword check, expected 8589934593, got %d", big);
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pass = 1'b0;
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end
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if (out !== 'b0) begin
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$display("Failed: initial value, expected 8'b0, got %b", out);
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pass = 1'b0;
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end
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in = 0.499999;
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bin = -25.5; // This test a different branch (small result -> big vec.).
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#1;
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if (big !== -26) begin
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$display("Failed: small value multiword check, expected -26, got %d", out);
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pass = 1'b0;
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end
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if (out !== 8'b0) begin
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$display("Failed: rounding value (down, +), expected 8'b0, got %b", out);
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pass = 1'b0;
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end
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in = -0.499999;
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#1;
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if (out !== 8'b0) begin
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$display("Failed: rounding value (down, -), expected 8'b0, got %b", out);
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pass = 1'b0;
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end
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in = 0.5;
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#1;
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if (out !== 8'b01) begin
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$display("Failed: rounding value (up, +), expected 8'b01, got %b", out);
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pass = 1'b0;
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end
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in = -0.5;
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#1;
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if (out !== 8'b11111111) begin
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$display("Failed: rounding value (up, -), expected 8'b11111111, got %b", out);
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pass = 1'b0;
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end
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in = 256.0;
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#1;
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if (out !== 8'b0) begin
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$display("Failed: overflow expected 8'b0, got %b", out);
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pass = 1'b0;
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end
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in = 511.0;
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#1;
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if (out !== 8'b11111111) begin
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$display("Failed: pruning expected 8'b11111111, got %b", out);
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pass = 1'b0;
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end
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in = 1.0/0.0;
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#1;
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if (out !== 8'bxxxxxxxx) begin
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$display("Failed: +inf expected 8'bxxxxxxxx, got %b", out);
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pass = 1'b0;
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end
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in = -1.0/0.0;
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#1;
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if (out !== 8'bxxxxxxxx) begin
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$display("Failed: -inf expected 8'bxxxxxxxx, got %b", out);
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pass = 1'b0;
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end
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in = $sqrt(-1.0);
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#1;
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if (out !== 8'bxxxxxxxx) begin
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$display("Failed: nan expected 8'bxxxxxxxx, got %b", out);
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pass = 1'b0;
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end
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in = 8589934720.5;
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#1;
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if (out !== 129) begin
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$display("Failed: overflow value expected 129, got %d", out);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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