31 lines
605 B
Verilog
31 lines
605 B
Verilog
// Incomplete case statements in asynchronous logic are dangerous in
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// synthesisable code, as in real hardware the inferred latch will be
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// sensitive to glitches as the case select value changes. Check that
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// the compiler outputs a warning for this.
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module mux(
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input wire [2:0] sel,
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input wire [2:0] i1,
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input wire [2:0] i2,
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input wire [2:0] i3,
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input wire [2:0] i4,
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output reg [2:0] o
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);
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(* ivl_synthesis_on *)
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always @* begin
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case (sel)
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0 : o = 0;
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1 : o = i1;
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2 : o = i2;
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3 : o = i3;
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4 : o = i4;
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endcase
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end
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(* ivl_synthesis_off *)
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initial $display("PASSED");
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endmodule
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