144 lines
3.1 KiB
Verilog
144 lines
3.1 KiB
Verilog
/*
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* Copyright (c) 2006 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*
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* $Id: casesynth3.v,v 1.1 2006/01/21 21:53:09 stevewilliams Exp $"
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*/
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/*
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* This case tests the handling very wide (but sparse) case statements.
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*/
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module main;
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reg clk, rst, set;
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reg [3:0] out, load;
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reg [10:0] op;
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(* ivl_synthesis_on *)
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always @(posedge clk or posedge rst)
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if (rst) begin
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out <= 0;
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end else if (set) begin
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out <= load;
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end else
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case (op)
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10'b0000000001: /* increment */ out <= out + 1;
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10'b1000000000: /* decrement */ out <= out - 1;
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10'b1000000001: /* Invert */ out <= ~out;
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/* Other ops cause out to not change. */
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endcase // case(mod)
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(* ivl_synthesis_off *)
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initial begin
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/* Test rst behavior. */
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op = 10'b0000000000;
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rst = 1;
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set = 0;
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load = 0;
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clk = 0;
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#1 clk = 1;
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#1 clk = 0;
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if (out !== 4'b0000) begin
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$display("FAILED -- out=%b (reset)", out);
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$finish;
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end
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/* Test set behavior */
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rst = 0;
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set = 1;
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load = 4'b0100;
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#1 clk = 1;
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#1 clk = 0;
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if (out !== 4'b0100) begin
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$display("FAILED -- out=%b (load)", out);
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$finish;
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end
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/* Test increment behavior */
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op = 10'b0000000001;
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rst = 0;
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set = 0;
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load = 0;
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#1 clk = 1;
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#1 clk = 0;
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if (out !== 4'b0101) begin
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$display("FAILED -- out=%b (increment 1)", out);
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$finish;
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end
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#1 clk = 1;
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#1 clk = 0;
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if (out !== 4'b0110) begin
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$display("FAILED -- out=%b (increment 2)", out);
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$finish;
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end
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/* Test invert behavior */
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op = 10'b1000000001;
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#1 clk = 1;
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#1 clk = 0;
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if (out !== 4'b1001) begin
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$display("FAILED == out=%b (invert)", out);
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$finish;
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end
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/* Test NO-OP behavior */
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op = 10'b0000000000;
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#1 clk = 1;
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#1 clk = 0;
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if (out !== 4'b1001) begin
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$display("FAILED -- out=%b (noop)", out);
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$finish;
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end
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/* Test decrement behavior */
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op = 10'b1000000000;
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#1 clk = 1;
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#1 clk = 0;
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if (out !== 4'b1000) begin
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$display("FAILED -- out=%b (decrement 1)", out);
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$finish;
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end
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#1 clk = 1;
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#1 clk = 0;
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if (out !== 4'b0111) begin
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$display("FAILED -- out=%b (decrement 2)", out);
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$finish;
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end
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$display("PASSED");
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$finish;
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end
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endmodule // main
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