47 lines
605 B
Verilog
47 lines
605 B
Verilog
module switch (q,a,b,c,d,sel);
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input a,b,c,d;
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input [1:0] sel;
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output q;
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reg q;
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always @ *
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case (sel)
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2'b00: q = a;
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2'b01: q = b;
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2'b10: q = c;
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2'b11: q = d;
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endcase
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endmodule
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module test ;
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reg [1:0] sel;
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reg a,b,c,d;
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wire q;
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switch u_switch (q,a,b,c,d,sel);
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initial
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begin
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a = 0;
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b = 0;
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c = 0;
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d = 0;
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sel = 2'b00;
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#1;
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if(q !== 1'b0)
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begin
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$display("FAILED");
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$finish;
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end
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a = 1;
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#1;
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if(q !== 1'b1)
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begin
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$display("FAILED");
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$finish;
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end
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$display("PASSED");
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end
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endmodule
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