66 lines
1.7 KiB
Verilog
66 lines
1.7 KiB
Verilog
//
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// Copyright (c) 1999 Steven Wilson (stevew@home.com)
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//
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// This source code is free software; you can redistribute it
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// and/or modify it in source code form under the terms of the GNU
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// General Public License as published by the Free Software
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// Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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//
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// SDW - Validate case/endcase w/ null_statement - no default
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module main ();
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reg error;
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reg [2:0] val1,val2;
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reg [2:0] result ;
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always @( val1 or val2)
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case (val1 & val2 )
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3'b000,3'b001: result = 0;
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3'b101: ;
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3'b011: result = 1;
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endcase
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initial
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begin
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error = 0;
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val1 = 3'b0;
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val2 = 3'b0;
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#1 if(result !==0)
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begin
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$display("FAILED case 3.8C - case (expr) lab1: ");
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error = 1;
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end
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val1 = 3'b111;
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val2 = 3'b011;
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#1 if(result !==1)
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begin
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$display("FAILED case 3.8C - case (expr) lab2: ");
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error = 1;
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end
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val2 = 3'b101; // Should activate null statement and get no action
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#1 if(result !==1)
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begin
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$display("FAILED case 3.8C - case (expr) lab1: ");
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error = 1;
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end
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if(error == 0)
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$display("PASSED");
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end
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endmodule // main
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