90 lines
1.2 KiB
Verilog
90 lines
1.2 KiB
Verilog
// Regression test for bug reported by Niels Moeller on 21-Mar-2015 via
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// iverilog-devel mailing list. Extended to cover similar problems. This
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// is just testing compiler error recovery.
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module test();
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integer array[3:0];
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integer i1;
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always @* begin
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for (i1 = 0; i1 < 4; i1 = i1 + 1) begin
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array[i1] = undeclared;
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end
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end
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integer i2;
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always @* begin
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for (i2 = 0; i2 < 4; i2 = i2 + 1) begin
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undeclared = array[i2];
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end
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end
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integer i3;
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always @* begin
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for (i3 = undeclared; i3 < 4; i3 = i3 + 1) begin
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array[i3] = i3;
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end
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end
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integer i4;
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always @* begin
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for (i4 = 0; i4 < undeclared; i4 = i4 + 1) begin
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array[i4] = i4;
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end
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end
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integer i5;
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always @* begin
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for (i5 = 0; i5 < 4; i5 = i5 + undeclared) begin
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array[i5] = i5;
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end
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end
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integer i6;
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always @* begin
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i6 = 0;
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while (i6 < undeclared) begin
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array[i6] = i6;
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i6 = i6 + 1;
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end
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end
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integer i7;
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always @* begin
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i7 = 0;
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while (i7 < 4) begin
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array[i7] = undeclared;
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i7 = i7 + 1;
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end
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end
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integer i8;
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always @* begin
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i8 = 0;
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repeat (undeclared) begin
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array[i8] = i8;
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i8 = i8 + 1;
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end
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end
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integer i9;
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always @* begin
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i9 = 0;
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repeat (4) begin
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array[i9] = undeclared;
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i9 = i9 + 1;
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end
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end
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endmodule
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