29 lines
563 B
Verilog
29 lines
563 B
Verilog
module top;
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logic clk = 0;
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int cnt = 0;
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always @(posedge clk) begin
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fork begin
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#(10*2); // Wait 10 clock periods
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cnt++;
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end
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join_none
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end
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initial begin
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$display("Starting test");
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repeat (100) begin
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#1 clk = 1;
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#1 clk = 0;
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end
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#(10*2); // Wait 10 clock periods
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$display("cnt = %0d", cnt);
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if (cnt === 100)
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$display("PASSED");
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else
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$display("FAILED");
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$finish(0);
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end
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endmodule
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