35 lines
560 B
Verilog
35 lines
560 B
Verilog
module tb();
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reg inputs[1:0];
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reg out;
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always @* begin
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if (inputs[1]) out = inputs[0];
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end
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reg failed;
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(* ivl_synthesis_off *)
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initial begin
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failed = 0;
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#1 inputs[1] = 1;
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#1 inputs[0] = 0;
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#1 $display(inputs[1],,inputs[0],,out);
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if (out !== 0) failed = 1;
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#1 inputs[1] = 0;
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#1 inputs[0] = 1;
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#1 $display(inputs[1],,inputs[0],,out);
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if (out !== 0) failed = 1;
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#1 inputs[1] = 1;
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#1 $display(inputs[1],,inputs[0],,out);
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if (out !== 1) failed = 1;
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if (failed)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule
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