33 lines
410 B
Verilog
33 lines
410 B
Verilog
module dut;
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integer id;
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endmodule
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module test;
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dut inst[4];
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integer i;
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reg failed = 0;
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initial begin
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inst[0].id = 0;
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inst[1].id = 1;
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inst[2].id = 2;
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inst[3].id = 3;
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if (inst[0].id !== 0) failed = 1;
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if (inst[1].id !== 1) failed = 1;
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if (inst[2].id !== 2) failed = 1;
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if (inst[3].id !== 3) failed = 1;
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if (failed)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule
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