37 lines
434 B
Verilog
37 lines
434 B
Verilog
package pkg;
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typedef enum logic [3:0] {
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ABC = 4'h1
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} enum_t;
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typedef struct packed {
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enum_t item;
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} w_enum;
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typedef struct packed {
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logic [3:0] item;
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} w_logic;
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typedef union packed {
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w_enum el1;
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w_logic el2;
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} foo_t;
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endpackage
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module main();
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import pkg::*;
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foo_t val;
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initial begin
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val.el1.item = ABC;
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if (val.el2.item === 4'h1)
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$display("PASSED");
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else
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$display("FAILED");
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end
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endmodule
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