21 lines
392 B
VHDL
21 lines
392 B
VHDL
-- Reduced test case, bug originally found in 4DSP's fmc110_ads5400_ctrl.vhd
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entity bug5 is
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port (
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clk : in std_logic;
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trig : in std_logic;
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data_o : out std_logic
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);
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end bug5;
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architecture bug5_syn of bug5 is
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begin
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dummy:process(clk)
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begin
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if (trig = '1') then
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--data_o <= '1'; -- uncomment this and everythings's OK
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end if;
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end process dummy;
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end bug5_syn;
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