54 lines
845 B
VHDL
54 lines
845 B
VHDL
-- Reduced test case, bug originally found in 4DSP's fmc110_ctrl.vhd
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library ieee;
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use ieee.std_logic_1164.all;
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entity bug3 is
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port (
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clk1_i : in std_logic;
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clk1_ib : in std_logic;
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clk1_o : out std_logic
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);
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end bug3;
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architecture bug3_syn of bug3 is
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component IBUFDS generic (
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DIFF_TERM : boolean := FALSE
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); port(
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O : out std_logic;
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I : in std_logic;
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IB : in std_logic
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); end component;
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begin
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ibufds1 : ibufds
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generic map (
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DIFF_TERM => TRUE -- change to "1" and vhdlpp is happy
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)
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port map (
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i => clk1_i,
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ib => clk1_ib,
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o => clk1_o
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);
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end bug3_syn;
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entity ibufds is
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generic (
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DIFF_TERM : boolean := FALSE
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);
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port (
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i : in std_logic;
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ib : in std_logic;
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o : out std_logic
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);
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end ibufds;
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architecture ibufds_sim of ibufds is
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begin
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o <= i;
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end ibufds_sim;
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