53 lines
803 B
Verilog
53 lines
803 B
Verilog
`timescale 1ns/10ps
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module TBUF_X2 (A, EN, Z);
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input A;
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input EN;
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output Z;
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bufif1(Z, A, EN);
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specify
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(A => Z) = (0.1, 0.2);
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(EN => Z) = (0.3, 0.4);
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endspecify
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endmodule
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module ckt (out, in, en);
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output out;
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input in, en;
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TBUF_X2 dut (.A ( in ) , .EN ( en ) , .Z ( out ) ) ;
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endmodule
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module top;
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wire out;
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reg in, en;
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ckt dut(out, in, en);
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initial begin
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$monitor($realtime,,out,"=",in,,en);
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$sdf_annotate("ivltests/br960c.sdf", dut);
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in = 1'b0;
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en = 1'b0;
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$display("Max (X->Z)");
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// X -> Z = max(enable))
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#10;
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en = 1'b1;
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$display("Z->0");
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#10;
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en = 1'b0;
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$display("0->Z");
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#5;
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in = 1'b1;
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#5;
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en = 1'b1;
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$display("Z->1");
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#10;
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en = 1'b0;
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$display("1->Z");
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#10;
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end
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endmodule
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