39 lines
442 B
Verilog
39 lines
442 B
Verilog
module driver(
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inout wire b0,
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inout wire b1
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);
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reg [1:0] v;
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buf (strong0, pull1) buf0(b0, v[0]);
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buf (strong0, pull1) buf1(b1, v[1]);
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initial begin
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v = 2'b10;
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end
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endmodule
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module br918c();
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wire [1:0] bus;
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pullup pu0(bus[0]);
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pullup pu1(bus[1]);
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driver driver(
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.b0 (bus[0]),
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.b1 (bus[1])
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);
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initial begin
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#1 $display("%b", bus);
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if (bus === 2'b10)
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$display("PASSED");
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else
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$display("FAILED");
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end
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endmodule
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