43 lines
714 B
Verilog
43 lines
714 B
Verilog
module test;
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bit b;
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bit [9:0] b10;
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bit signed bs;
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bit unsigned bu;
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bit signed [6:0] bs7;
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bit unsigned [5:0] bu6;
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initial
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begin
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b = 1;
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b10 = 100;
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bs = 0;
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bu = 1;
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bs7 = -17;
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bu6 = 21;
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#1;
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if (b * b10 !== 100) begin
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$display ("FAILED 1");
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$finish;
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end
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if (bs * b10 !== 0) begin
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$display ("FAILED 2" );
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$finish;
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end
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if (bu * b10 !== 100) begin
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$display ("FAILED 3");
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$finish;
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end
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if (bs7 * 1 !== -17) begin
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$display ("FAILED 4");
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$finish;
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end
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if (bu6 * b !== 21) begin
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$display ("FAILED 5");
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$finish;
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end
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$display ("PASSED");
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end
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endmodule
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