38 lines
1.2 KiB
Verilog
38 lines
1.2 KiB
Verilog
//
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// Copyright (c) 1999 Steven Wilson (stevew@home.com)
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//
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// This source code is free software; you can redistribute it
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// and/or modify it in source code form under the terms of the GNU
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// General Public License as published by the Free Software
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// Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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//
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// SDW - Validate always assign reg_lvalue = boolean_expression ;
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// D: Note that initial has to be before always to execute!
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module main ;
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reg [3:0] value1 ;
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initial
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if(value1 != 4'h1)
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$display("FAILED - 3.1.3B always assign reg_lvalue = boolean_expr\n");
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else
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begin
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$display("PASSED\n");
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$finish;
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end
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always assign value1 = 1'b1 && 1'b1 ;
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endmodule
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