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iverilog/tgt-vhdl
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Nick Gasson 4263f791f6 Fix part select of width-1 vector 
Signals of width 1 are declared in VHDL as std_logic, as this
is the usual way to represent them. Unfortunately, we cannot
distinguish between

reg [0:0] a;

and

reg a;

This patch avoids trying to slice a std_logic so a[0] is equivalent to a.
 		2008-11-26 13:14:27 -08:00
..
vhpi Move the VHDL support package 2008-07-07 15:36:13 +01:00
Makefile.in Update Makefile.in to have current version by default. 2008-11-25 16:42:32 -08:00
cast.cc Shadow reduction part 4 2008-10-30 21:46:44 -07:00
configure.in Remove the unused CVS ident support in the configure scripts. 2008-11-19 21:07:34 -08:00
display.cc Shadow reduction part 4 2008-10-30 21:46:44 -07:00
expr.cc Fix select from non-variable-reference error (pr2281519) 2008-11-15 20:39:00 -08:00
logic.cc Spelling fixes 2008-09-09 19:21:42 -07:00
lpm.cc Fix part select of width-1 vector 2008-11-26 13:14:27 -08:00
process.cc Use ivl_process_* functions for file/line number information 2008-08-02 10:44:03 +01:00
scope.cc VHDL make comment for temporaries unique. 2008-11-18 20:28:28 -08:00
stmt.cc Fix part select of width-1 vector 2008-11-26 13:14:27 -08:00
support.cc Tidy up reduction functions in support.cc 2008-09-13 18:20:12 +01:00
support.hh Tidy up reduction functions in support.cc 2008-09-13 18:20:12 +01:00
vhdl-s.conf Cary R.'s additional system functions, real value error messages, etc. 2008-09-06 12:06:01 +01:00
vhdl.cc Add converter info to VHDL output. 2008-11-19 20:44:34 -08:00
vhdl.conf Remove redundant back-end selections. 2008-09-07 16:43:54 -07:00
vhdl_config.h.in Makefile and autoconf changes to build VHDL code generator 2008-05-28 17:17:39 +01:00
vhdl_element.cc Compress support function definitions a bit 2008-07-19 21:04:52 +01:00
vhdl_element.hh Compress support function definitions a bit 2008-07-19 21:04:52 +01:00
vhdl_helper.hh Handle '?' in vl_to_vhdl_bit 2008-08-11 13:53:42 +01:00
vhdl_syntax.cc Add casex/z support 2008-10-14 20:16:10 +01:00
vhdl_syntax.hh Add casex/z support 2008-10-14 20:16:10 +01:00
vhdl_target.h Avoid generating useless `wait for 0ns' statements 2008-08-05 11:02:36 +01:00
vhdl_type.cc Generate VHDL array type declarations of Verilog arrays 2008-07-17 13:08:55 +01:00
vhdl_type.hh Generate VHDL array type declarations of Verilog arrays 2008-07-17 13:08:55 +01:00