28 lines
355 B
Verilog
28 lines
355 B
Verilog
`timescale 1s/1ms
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module test;
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reg [7:0] a, b;
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initial begin
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a = 0; b = 0;
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$monitor_time_slot(2000, a, b);
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$monitor_time_slot(5000, a, b);
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#1;
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a = 1; b <= 1;
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#1;
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a = 2; b <= 2;
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#1;
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a = 3; b <= 3;
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#1;
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a = 4; b <= 4;
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#1;
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a = 5; b <= 5;
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#1;
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a = 6; b <= 6;
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#1;
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$finish(0);
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end
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endmodule
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