24 lines
374 B
Verilog
24 lines
374 B
Verilog
module main;
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reg [5*8-1 : 0] hello;
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initial begin
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hello = "XXXXX";
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if (hello !== "XXXXX") begin
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$display("FAILED -- X = %h", hello);
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$finish;
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end
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$hello_poke(hello);
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if (hello !== "Hello") begin
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$display("FAILED -- Hello = %h", hello);
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$finish;
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end
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$display("PASSED");
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end // initial begin
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endmodule // main
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