30 lines
743 B
Verilog
30 lines
743 B
Verilog
// Check that partial module ANSI port declarations are supported. Check that it
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// is possible to redefine the unpacked dimensions only.
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module test (input integer a, b[1:0], c[2:0][3:0]);
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bit failed = 1'b0;
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`define check(val, exp) do begin \
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if ((val) !== (exp)) begin \
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$display("FAILED(%0d): Expected `%d`, got `%d`.", `__LINE__, \
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(exp), (val)); \
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failed = 1'b1; \
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end \
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end while (0)
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initial begin
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`check($dimensions(a), 1);
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`check($dimensions(b), 2);
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`check($dimensions(c), 3);
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`check($bits(a), $bits(integer));
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`check($bits(b), $bits(integer) * 2);
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`check($bits(c), $bits(integer) * 3 * 4);
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if (!failed) begin
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$display("PASSED");
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end
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end
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endmodule
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