19 lines
357 B
Verilog
19 lines
357 B
Verilog
// Check that const variables in module scope are supported.
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module test;
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const integer x = 10;
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// The initializer expression is allowed to reference other const variables.
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const integer y = 20 + x;
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initial begin
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if (x === 10 && y === 30) begin
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$display("PASSED");
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end else begin
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$display("FAILED");
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end
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end
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endmodule
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