70 lines
952 B
Verilog
70 lines
952 B
Verilog
`timescale 1ns/1ps
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/*
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This design tests the interconnection delay
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for three buffers in parallel
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*/
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module buffer (
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input in,
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output out
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);
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specify
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(in => out) = (0.0:0.0:0.0);
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endspecify
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assign out = in;
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endmodule
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module my_design (
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input a,
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output b
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);
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wire w1, w2, w3;
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buffer buffer0 (
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.in (a),
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.out (w1)
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);
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buffer buffer1 (
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.in (a),
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.out (w2)
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);
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buffer buffer2 (
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.in (a),
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.out (w3)
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);
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assign b = w1 & w2 & w3;
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endmodule
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module top;
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reg a;
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wire b;
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initial begin
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$sdf_annotate("ivltests/sdf_interconnect2.sdf", my_design_inst);
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$monitor("time=%0t a=%h b=%h", $realtime, a, b);
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end
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initial begin
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#5;
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a <= 1'b0;
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#10;
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a <= 1'b1;
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#10;
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$finish;
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end
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my_design my_design_inst (
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.a (a),
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.b (b)
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);
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endmodule
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