iverilog/ivtest/ivltests/br_gh1175f.v

12 lines
185 B
Verilog

primitive id_0(output reg id_2, input id_1);
table
0 : 0 : 0;
endtable
endprimitive
primitive id_0(output reg id_2, input id_1);
table
1 : 0 : 0;
endtable
endprimitive