52 lines
989 B
Verilog
52 lines
989 B
Verilog
// Check that variables referenced in a void function contribute to the
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// sensitivity list of a always_comb block.
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module top;
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logic passed;
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logic [7:0] value;
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integer counter;
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function automatic void count(bit what);
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counter = 0;
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for (integer i = 0; i < $bits(value); i++) begin
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if (value[i] == what)
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counter += 1;
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end
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endfunction
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always_comb begin
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count(1'b1);
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end
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initial begin
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passed = 1'b1;
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value = 8'b0000_0000;
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#1;
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if (counter !== 0) begin
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$display("Expected 0, got %d", counter);
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passed = 1'b0;
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end
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value = 8'b0011_1100;
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#1;
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if (counter !== 4) begin
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$display("Expected 4, got %d", counter);
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passed = 1'b0;
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end
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value = 8'b1011_1101;
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#1;
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if (counter !== 6) begin
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$display("Expected 6, got %d", counter);
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passed = 1'b0;
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end
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if (passed) begin
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$display("PASSED");
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end else begin
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$display("FAILED");
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end
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end
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endmodule
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