37 lines
1.0 KiB
ReStructuredText
37 lines
1.0 KiB
ReStructuredText
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The VVP Target
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==============
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Symbol Name Conventions
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-----------------------
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There are some naming conventions that the vvp target uses for
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generating symbol names.
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* wires and regs
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Nets and variables are named V_<full-name> where <full-name> is the
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full hierarchical name of the signal.
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* Logic devices
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Logic devices (and, or, buf, bufz, etc.) are named L_<full_name>. In
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this case the symbol is attached to a functor that is the output of
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the logic device.
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General Functor Web Structure
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-----------------------------
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The net of gates, signals and resolvers is formed from the input
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design. The basic structure is wrapped around the nexus, which is
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represented by the ivl_nexus_t.
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Each nexus represents a resolved value. The input of the nexus is fed
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by a single driver. If the nexus in the design has multiple drivers,
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the drivers are first fed into a resolver (or a tree of resolvers) to
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form a single output that is the nexus.
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The nexus, then, feeds its output to the inputs of other gates, or to
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the .net objects in the design.
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