/* * Copyright (c) 2001-2009 Stephen Williams (steve@icarus.com) * */ EXECUTABLE INSTRUCTION OPCODES Instruction opcodes all start with a % character and have 0 or more operands. In no case are there more than 3 operands. This chapter describes the specific behavior of each opcode, in enough detail (I hope) that its complete effect can be predicted. General principles of Arithmetic: The binary arithmetic instruction in general takes three parameters, the left operand, the right operand, and the base. The left operand is replaced with the result, which is the same width as the left and right operands. * %abs/wr , This instruction calculates the absolute value of a real value. It uses the fabs() function in the run-time to do the work. * %add , , This instruction adds the right vector into the left vector, the vectors having the width . If any of the bits of either vector are x or z, the result is x. Otherwise, the result is the arithmetic sum. See also the %sub instruction. * %add/wr , This is the real valued version of the %add instruction. The arguments are word indices of the operands. The right operand is added into the left operand. See also the %sub/wr instruction. * %addi , , This instruction adds the immediate value (no x or z bits) into the left vector. The imm value is limited to 16 significant bits, but it is zero extended to match any width. * %alloc This instruction allocates the storage for a new instance of an automatically allocated scope. * %and , , Perform the bitwise AND of the two vectors, and store the result in the left vector. Each bit is calculated independent of other bits. AND means the following: 0 and ? --> 0 ? and 0 --> 0 1 and 1 --> 1 otherwise x * %assign/av , , * %assign/av/d , , * %assign/av/e , The %assign/av instruction assigns a vector value to a word in the labeled array. The is the delay in simulation time to the assignment (0 for non-blocking assignment) and the is the base of the vector to write. The width of the vector is retrieved from index register 0. The base of a part select is retrieved from index register 1. The address of the word in the memory is from index register 3. The address is canonical form. The %assign/av/d variation reads the delay from an integer register that is given by the value. This should not be 0, 1 or 3, of course, since these registers contain the vector width, base part select and word address. The %assign/av/e variation uses the information in the thread event control registers to determine when to perform the assign. %evctl is used to set the event control information. * %assign/v0 , , * %assign/v0/d , , * %assign/v0/e , The %assign/v0 instruction is a vector version of non-blocking assignment. The is the number of clock ticks in the future where the assignment should be schedule, and the is the base of the vector to be assigned to the destination. The vector width is in index register 0. The %assign/v0/d variation gets the delay instead from an integer register that is given by the value. This should not be 0, of course, because integer 0 is taken with the vector width. The %assign/v0/e variation uses the information in the thread event control registers to determine when to perform the assign. %evctl is used to set the event control information. The references a .var object that can receive non-blocking assignments. For blocking assignments, see %set/v. * %assign/v0/x1 , , * %assign/v0/x1/d , , * %assign/v0/x1/e , This is similar to the %assign/v0 instruction, but adds the index-1 index register with the canonical index of the destination where the vector is to be written. This allows for part writes into the vector. * %assign/wr , , * %assign/wr/d , , * %assign/wr/e , This instruction provides a non-blocking assign of the real value given in to the real object addressed by the label after the given . The %assign/wr/d variation gets the delay from integer register . The %assign/wr/e variation uses the information in the thread event control registers to determine when to perform the assign. %evctl is used to set the event control information. * %assign/x0 , , (OBSOLETE -- See %assign/v0x) This does a non-blocking assignment to a functor, similar to the %assign instruction. The identifies the base functor of the affected variable, and the gives the delay when the assignment takes place. The delay may be 0. The actual functor used is calculated by using as a base, and indexing with the index[0] index register. This supports indexed assignment. The is the address of the thread register that contains the bit value to assign. * %blend , , This instruction blends the bits of a vector into the destination in a manner like the expression (x ? : ). The truth table is: 1 1 --> 1 0 0 --> 0 z z --> z x x --> x .... --> x In other words, if the bits are identical, then take that value. Otherwise, the value is x. * %blend/wr , This instruction blends real values for the ternary operator. If the values match return that otherwise return 0.0. * %breakpoint This instruction unconditionally breaks the simulator into the interactive debugger. The idea is to stop the simulator here and give the user a chance to display the state of the simulation using debugger commands. This may not work on all platforms. If run-time debugging is compiled out, then this function is a no-op. * %cassign/v , , Perform a continuous assign of a constant value to the target variable. This is similar to %set, but it uses the cassign port (port-1) of the signal functor instead of the normal assign, so the signal responds differently. See "VARIABLE STATEMENTS" in the README.txt file. * %cassign/wr , Perform a continuous assign of a constant real value to the target variable. See %cassign/v above. * %cassign/x0