$date
	Fri Jun 19 15:35:19 2026
$end
$version
	Icarus Verilog
$end
$timescale
	1s
$end
$scope module evcd_basic.u $end
$var port 1 <0 a $end
$var port 1 <1 b $end
$var port 1 <2 y $end
$var port 1 <3 io $end
$upscope $end
$enddefinitions $end
#0
$dumpports
pD 6 0 <0
pD 6 0 <1
pL 6 0 <2
pF 0 0 <3
$end
#5
pU 0 6 <0
p0 6 0 <3
#10
pU 0 6 <1
p1 0 6 <3
pH 0 6 <2
#15
pD 6 0 <0
pF 0 0 <3
pL 6 0 <2
#20