:ivl_version "12.0" "vec4-stack";
:vpi_module "system";

; Copyright (c) 2001-2015  Stephen Williams (steve@icarus.com)
;
;    This program is free software; you can redistribute it and/or modify
;    it under the terms of the GNU General Public License as published by
;    the Free Software Foundation; either version 2 of the License, or
;    (at your option) any later version.
;
;    This program is distributed in the hope that it will be useful,
;    but WITHOUT ANY WARRANTY; without even the implied warranty of
;    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
;    GNU General Public License for more details.
;
;    You should have received a copy of the GNU General Public License along
;    with this program; if not, write to the Free Software Foundation, Inc.,
;    51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.

; This example slightly extends the hello.vvp example by adding the
; set and display of a reg variable. The Verilog source that would
; make this might be:
;
;    module main;
;       reg [3:0] value1;
;       initial begin
;          value1 = 1;
;          $display("value = %b", value1);
;       end
;    endmodule
;
; Notice that the var "value1" is placed into the "main" scope simply
; by having main current when the .var statement is compiled. And also
; notice that the Vmain.value1 label is automatically converted to a
; vpiHandle by the compiler when the %vpi_call statement is compiled.


Smain    .scope module, "main" "main" 0 0;

Vmain.value1	.var "value1", 3 0;

T00	%pushi/vec4 1, 0, 4;  Push a 4 bit value (1) on the stack
        %store/vec4 Vmain.value1, 0, 4;

	%vpi_call 0 0 "$display", "value = %b", Vmain.value1 {0 0 0};

	%end;

	.thread T00;
:file_names 2;
    "N/A";
    "<interactive>";