module check (input unsigned [22:0] a, b, input unsigned [45:0] c); wire unsigned [45:0] int_AB; assign int_AB = a * b; always @(a, b, int_AB, c) begin #1; if (int_AB !== c) begin $display("ERROR"); $finish; end end endmodule module stimulus (output reg unsigned [22:0] A, B); parameter MAX = 1 << 23; parameter S = 10000; int unsigned i; initial begin A = 0; B= 0; for (i=0; i