module check (input unsigned [103:0] a, b, c); wire [103:0] int_AB; assign int_AB = ~(a & b); always @(a, b, int_AB, c) begin #1; if (int_AB !== c) begin $display("ERROR"); $finish; end end endmodule module stimulus (output reg unsigned [103:0] A, B); parameter S = 2000; int unsigned i; initial begin A = 0; B= 0; // values with 0, 1 for (i=0; i