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Contributor": [[0, "getting-started-as-a-contributor"]], "Getting Icarus Verilog": [[0, "getting-icarus-verilog"]], "Icarus Specific Configuration Options": [[0, "icarus-specific-configuration-options"], [47, "icarus-specific-configuration-options"]], "Compiling on Linux": [[0, "compiling-on-linux"]], "Regression Tests": [[0, "regression-tests"]], "Forks, Branches and Pull Requests": [[0, "forks-branches-and-pull-requests"]], "Glossary": [[1, "glossary"]], "Cadence PLI1 Modules": [[2, "cadence-pli1-modules"]], "Developer Guide": [[3, "developer-guide"]], "Compiler Components": [[3, "compiler-components"]], "Runtime Components": [[3, "runtime-components"]], "The Core Compiler": [[3, "the-core-compiler"]], "Further Reading": [[3, "further-reading"]], "Icarus Verilog Attributes": [[4, "icarus-verilog-attributes"]], "Attribute Naming Conventions": [[4, "attribute-naming-conventions"]], "Attributes To Control Synthesis": [[4, "attributes-to-control-synthesis"]], "Misc": [[4, "misc"]], "IVL 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"memories"]], "Expressions": [[8, "expressions"]], "Expression Bit Width": [[8, "expression-bit-width"]], "Interaction Of Expressions And Structure: NetESignal": [[8, "interaction-of-expressions-and-structure-netesignal"]], "Hierarchy In Netlists": [[8, "hierarchy-in-netlists"]], "Scope Representation In Netlists": [[8, "scope-representation-in-netlists"]], "Tasks In Netlists": [[8, "tasks-in-netlists"]], "Time Scale In Netlists": [[8, "time-scale-in-netlists"]], "Loadable Targets": [[9, "loadable-targets"]], "Loading Target Modules": [[9, "loading-target-modules"]], "Loadable Target Module Api": [[9, "loadable-target-module-api"]], "About Specific Expression Types": [[9, "about-specific-expression-types"]], "IEEE1364 Notes": [[10, "ieee1364-notes"]], "Standardization Issues": [[10, "standardization-issues"]], "Miscellaneous": [[11, "miscellaneous"]], "Swift Model Support (Preliminary)": [[12, "swift-model-support-preliminary"]], "Xilinx Hint": [[13, "xilinx-hint"]], "Verilog:": [[13, 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Test Suite": [[25, "the-regression-test-suite"]], "Test Descriptions": [[25, "test-descriptions"]], "source (required)": [[25, "source-required"]], "type (required)": [[25, "type-required"]], "gold (optional)": [[25, "gold-optional"]], "iverilog-args (optional)": [[25, "iverilog-args-optional"]], "vvp-args (optional)": [[25, "vvp-args-optional"]], "vvp-args-extended (optional)": [[25, "vvp-args-extended-optional"]], "Files With Version Information": [[26, "files-with-version-information"]], "Icarus Verilog": [[27, "icarus-verilog"]], "Contents:": [[27, null]], "Indices and tables": [[27, "indices-and-tables"]], "The Icarus Verilog Targets": [[28, "the-icarus-verilog-targets"]], "The BLIF Code Generator (-tblif)": [[29, "the-blif-code-generator-tblif"]], "USAGE": [[29, "usage"]], "LIMITATIONS": [[29, "limitations"]], "The FPGA Code Generator (-tfpga)": [[30, "the-fpga-code-generator-tfpga"]], "INVOKING THE FPGA TARGET": [[30, "invoking-the-fpga-target"]], "XNF ROOT PORTS": [[30, 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