Add "include" to fix error with abort() in dup_expr.cc
Add "include" to AStatement.h so usage of struct PExpr works
Get rid of eval_tree.cc:577: warning: suggest parentheses around comparison in operand of ^
The right shift of vvp_vector2_t needs to
account for and mask off shifted bits. Otherwise
there will be unexpected results after
a vvp_vector2_t::trim method.
This patch adds the constant system functions for Verilog-2005
and Verilog-AMS. These are evaluated at compile time. $abs(),
$min() and $max() support their polymorphic behavior in the
compiler where it really matters. They are always evaluated
as reals in the run time and the result/argument(s) will be
converted as needed.
The Verilog-2005 functions are available if using the 2005
generation (default) and if either the icarus-misc (also on
by default) or verilog-ams flags are set.
The Verilog-AMS functions are available if either the
icarus-misc or verilog-ams flags are set.
If the argument to $clog2() is unsized constant, then trim it to the
smallest representation that doesn't lose the sign, then do the $clog2
on that.
Also, use integer_width instead of 32 for the minimum $clog2() result
for a negative value.
If the argument to $clog2() is unsized constant, then trim it to the
smallest representation that doesn't lose the sign, then do the $clog2
on that.
Also, use integer_width instead of 32 for the minimum $clog2() result
for a negative value.
This patch moves the always zero or possibly zero delay checks
to a point after the circuit is full elaborated. Before it
could try to check tasks that had not already been evaluated
resulting in a crash.
When looking for a delay_type() in a block stop when we have a
DEFINITE_DELAY. Doing this could reduce the number of statements
that need to be checked.
Previously only signedness was only corrected for the
result. This patch ensures the VHDL operands have the
same signedness as their Verilog counterparts.
This fixes a few of the signedX tests.
Assume that anything that is strength aware already handles a
recv_vec8_pv and make the default function convert the bits
to a vec4 and then call recv_vec4_pv with this new value.
It is legal for a task to have no definition. In that case, the
delay_type calculations (used to detect infinite loops) can assume
that an empty definition is a no-op and return NO_DELAY.
Be more sophisticated with the code generated for constant values.
When values are large, use an optimal mix of %movi and %mov
instructions to get the desired value, no matter what the content.
This splits up the monolithic and confusing vhdl_expr::cast function into
several smaller to_XXX functions which each generate code to cast an
expression to type XXX. This makes it much easier to understand and maintain.
In continuous assignment, the width of the expression needs to come
from the expression itself, and not just from the width of the l-value.
Use the PExpr::test_width method to get the width of the expression
to pass to the elaborate.
the sub_net_from function is used by the ::synthesize method of the
NetEUnary class to make the expression 0-N. By making that function
handle a real-valued net, the NetEUnary suddenly supports real-valued
nets, and this probably helps in other places as well.
When the condition expression of a ternary is constant 1 or 0, we can
short-circuit the elaboration by only processing the clause (true or
false) that we need. This saves compile time and execution time.
This patch adds an error message for the standard system
tasks and functions that are not currently implemented.
These are currently $fmonitor*, $ferror, $fread, the
queue and PLA tasks.
Stephen Williams
Nick Gasson
Cary R
Larry Doolittle