Continue cleaning up shadowed variables, flagged by turning on -Wshadow.
No intended change in functionality. This patch set covers the tgt-vhdl
directory, and was tested by Nick.
This patch fixes some problems found when trying to dump words
from a real wire array. There are still a few more things that
look suspicious and need testing.
This patch splits any VVP net functor that needs to access both
statically and automatically allocated state into two sub-classes,
one for handling operations on statically allocated state, the
other for handling operations on automatically allocated state.
This undoes the increase in run-time memory use introduced when
automatic task/function support was first introduced.
This patch also fixes various issues with event handling in automatic
scopes. Event expressions in automatic scopes may now reference either
statically or automatically allocated variables or arrays, or part
selects or word selects thereof. More complex expressions (e.g.
containing arithmetic or logical operators, function calls, etc.) are
not currently supported.
This patch introduces some error checking for language constructs
that may not reference automatically allocated variables. Further
error checking will follow in a subsequent patch.
The arguments of logical and/or are self determined, and the width is
fixed as 1 bit. Account for this special behavior by creating the
PEBLogic class.
The comparison operator operands are self determined, but are forced
to be the width of the wider operand. This means that the operands must
be evaluated with their widths truncated. In spite of all this, note
that comparisons expression results are 1 bit wide.
The operands of divide need to be at least the width of the expression
when calculating a constant divide. The only matters for the special
case where the result is x, because the verinum implementation of
divide will get the result width from the left expression width.
Now that NetNet objects in NetScopes are kept in a map, remove the
linked list for scanning them. This improves the lookup process from
an O(e**N) process to more like O(log(N)). This matters for very
large designs.
Get at least basic elaboration of analog processes and contribution
statements. Bring the statements and analog statements together and
net future elaboration work sort out which statements are valid in
a given context. This makes sense because there really is a lot of
syntactic overlap, and analog behavioral code is processed somewhat
sequentially.
Put together the infrastructure for elaborating analog statements,
including create the NetAnalogTop objects that hold analog statements
and are in turn held by the design.
While doing this, clean up the various unique initial/always enumerations
to use the ivl_process_type_t type.
The optimization that allowed a mux that had one input always
connected to high-Z produces code that is actually slower than
the original mux, so for now we are removing that optimization.
Continue cleaning up shadowed variables, flagged by turning on -Wshadow.
No intended change in functionality. Patch looks right, and is tested
to compile and run on my machine. No regressions in test suite.
The bufif devices do not correctly propagate the Z value as
required by the standard. The MOS devices do propagate a Z
value, but they do not correctly handle the case where both
inputs are Z and the select is undefined/Z. The standard
specifies that this should be X, but we produce Z. The full
MUX and %blend operator also function this way, so Icarus
may not match the standard, but it is consistent. I would
also argue that the standard is incorrect. If both inputs
are Z then the output should be Z no matter what select is.
The condition expression needs its width tested, even if the width
is not used. Also clean up some handling of widths/types for other
expression types.
This fixes the sign calculation for port padding. It also reports if
the padding will be signed or not in the warning message. The inout
calculation may not be correct. It requires both the signal and the
port to be signed, but inout is not currently padded anyway.
If a part select (either a constant or constant indexed part select)
of a L-value is fully outside the signal the part select will be
omitted after printing a warning. If a part select straddles the
upper portion of a signal a warning will be printed. The run time
will use only the appropriate part of the select. Straddling the
lower part of the signal is not currently supported and a message
is printed for this case.
The right-operand of shift expressions is self-determined, but we still
need to run a test_width to get the PExpr decorated with types and
expression widths.
A casex statement cannot be directly translated to a VHDL case
statement as VHDL does not treat the don't-care bit as special.
The solution here is to generate an if statement from the casex
which compares only the non-don't-care bit positions.
The l-value doesn't really constrain the size of unsized expressions
because there are possible sub-expressions that may pull high bits
down to the low bits. (Divide, for example.)
It is possible, via the use of the $signed() function, for concatenation
expressions to be signed. Make sure the evaluated constant had the
proper sign by checking explicitly.
Continue cleaning up shadowed variables, flagged by turning on -Wshadow.
No intended change in functionality. Patch looks right, and is tested
to compile and run on my machine. No regressions in test suite.
This patch modifies the code that finds and combines similar events
such that if similar events are found in both static and automatic
scopes, the retained event will be in a static scope. This is a
performance enhancement, as VVP has more run-time overhead when
handling events declared in an automatic scope.
This code was likely never checked properly since it makes no
sense to copy the expression from the new temporary system
function. You must copy the value from the current function.
Even on 64 bit machines immediate values should be limited to
32 bits so that the a.out file will run correctly on a 32 bit
machine. This patch fixes a number of places where the code
generator was not checking for/observing this.
The signedness of comparison expressions is typically unsigned, even if
the comparison to be performed is signed. The comparison (and particularly
the expr_synth of the comparison) needs to account for this explicitly.
If either of the operands of a ternary expression are unsigned, then
both are treated as unsigned. It works just like a binary expression
in that regard.
It is up to the elaborator to sign-extend the inputs if the multiply
is signed in the Verilog source. The run time always processes the
multiply as unsigned.
The results of comparisons are unsigned, but the arguments may be signed
and the calculation performed may be signed. Handle the padding properly
for comparisons so that the math is properly signed.
Larry Doolittle
Cary R
Stephen Williams
Nick Gasson
Martin Whitaker