Commit Graph

5188 Commits

Author SHA1 Message Date
Nick Gasson 8e023d1227 Remove redundant function 2008-08-22 21:27:24 +01:00
Nick Gasson d21b3258e3 Support conversion of (un)signed to std_logic
Take the least-significant bit. This fixes a couple of broken
test cases.
2008-08-22 20:59:14 +01:00
Nick Gasson 331a51e842 Add more warnings about untranslatable constructs 2008-08-22 20:25:58 +01:00
Nick Gasson 63a1e25129 Catch case where component name and instance differ only in case
This causes an error in VHDL (which is case-insensitive). This 
patch simply appends _Inst to the instance name if it detects this.
2008-08-22 20:20:17 +01:00
Nick Gasson fae7ab2418 Use case-insensitive string comparison for get_decl
This will allow us to detect cases where identifiers differ only by case
2008-08-22 20:15:45 +01:00
Stephen Williams 65a4f36de5 Watch out for left operand of left shift that is not known early.
It is possible for the left operand of a left shift to be not known
early during elaborate expression. In that case, make a punt expression
and expect it to be resolved later.
2008-08-21 18:58:38 -07:00
Stephen Williams 04d49fcf35 Merge branch 'master' into elaborate-net-rework 2008-08-21 18:11:21 -07:00
Nick Gasson 535ef6be38 Change function return value from Verilog_Result to <funcname>_Result 2008-08-21 19:44:12 +01:00
Nick Gasson d3b7d7a13d Merge branch 'master' of git://icarus.com/~steve-icarus/verilog into vhdl 2008-08-21 18:35:54 +01:00
Nick Gasson b92b62a8fb Include cstring required for GCC 4.3
GCC 4.3 has tightened up header dependencies so that
`strcmp' is no longer declared if <cstdlib> is included
(which it was in prior versions). This causes the changes
in 5e512e6570 to fail to
build with 4.3.

This patch includes <cstring> in the files that are failing.
2008-08-21 09:36:03 -07:00
Cary R 7eb34013dd Add vpip_calc_clog2 to vvp.def file
This is needed to get cygwin to compile correctly.
2008-08-21 09:34:33 -07:00
Stephen Williams e18eb32d8b Process shift by constant amounts early in expression elaboration.
The expr:::synthesize methods need not deal with saturating left or
right shifts if they are dealt with early, in elaborate_expr methods.
So the elaborate_expr for shift takes on much more responsibility.
2008-08-20 21:47:07 -07:00
Nick Gasson 4ebe09bb72 Various fixes to support automatic functions
Mostly this ensures that a recursive call to a function
is made with the correct types (this may involve generating
code to cast expressions to the correct type).
2008-08-20 22:54:53 +01:00
Nick Gasson a07dc968e7 Merge branch 'master' of git://icarus.com/~steve-icarus/verilog into vhdl 2008-08-20 18:58:46 +01:00
Stephen Williams 28991d30f4 Fix some ambiguous casts. 2008-08-20 09:40:16 -07:00
Cary R 11109f519c Push the automatic property for tasks and functions to the code gen.
This patch pushes the automatic property for both tasks and
functions to the code generators. The vvp back end does not
currently support this so it will error out during code
generation. The VHDL back end should be able to use this
property and tgt-stub prints the property. Having this will
also make it easier when we do adding this to the runtime.
2008-08-20 09:23:14 -07:00
Cary R 5e512e6570 Finish $clog2 function.
This patch fixes problems in the initial $clog2 implementation
and adds correct functionality to the runtime.
2008-08-20 09:01:21 -07:00
Cary R c032d28aaa Convert the infinities to 'bx
This patch modifies the double to vector conversions to return
'bx for either +/- infinity.
2008-08-20 09:01:09 -07:00
Cary R 768633e464 Add $clog2 function.
This patch adds the $clog2 system function. It also makes this
function work as a constant function. The runtime version still
needs to be updated to use an integer based version instead of
the current double based method. The double method suffers from
rounding errors.
2008-08-20 08:59:36 -07:00
Cary R e501bbdd27 Fix problems in VPI callback time and value formats.
This patch adds support for vpiScaledRealTime and vpiSuppressTime
to VPI callbacks. It also fixes a bug where the callback data
object was not being copied correctly and adds support for
vpiSuppressVal. This requires adding vpiSuppressVal to a few
other routines. It adds the ability for a callback to return
more than vpiScalarVal (all values supported by the
vpip_vec4_get_value() procedure). It also fixes a bug where
vpip_vec4_get_value() would incorrectly return vpiZ for a BIT4_X
scalar value. It also comments the potentially dangerous
vpiScalarVal calculation in the vvp_fun_signal::get_value()
procedure.
2008-08-20 08:52:09 -07:00
Nick Gasson cb1d4fd278 Amend inaccurate comment 2008-08-18 16:15:05 +01:00
Nick Gasson e1deba51ab Handle BUFIF logic when vector inputs 2008-08-18 15:48:07 +01:00
Nick Gasson d53014a07f Fix leading comma it expression only has "others" part
Stop syntax errors caused by things like this:
  (, others => '1')
2008-08-18 15:36:11 +01:00
Nick Gasson 7865264de0 Implement IVL_LPM_REPEAT 2008-08-18 15:34:58 +01:00
Nick Gasson 86661c1538 Add a few more `unsupported' messages 2008-08-18 15:29:30 +01:00
Nick Gasson e2dd7425bd Add error messages for unsupported statement types 2008-08-18 15:24:38 +01:00
Nick Gasson e01b16e586 Merge branch 'master' of git://icarus.com/~steve-icarus/verilog into vhdl 2008-08-18 15:16:02 +01:00
Nick Gasson 6adc3c9f13 Add short section on VHDL to man page 2008-08-17 19:42:07 +01:00
Stephen Williams 0de2dcb211 Allow elaborate_expr to handle implicit nets.
When the elaborate_expr code is used for expressions of continuous
assignments, it needs to be able to create implicit nets.
2008-08-17 08:22:42 -07:00
Stephen Williams a8ad505af7 Various improgements to expression ::synthesize methods
Since NetExpr::synthesize methods were rarely used, then had a lot
of bugs. Now that continuous assign uses these methods, these bugs
must be fixed.

Binary and Unary minus properly pad/extens its arguments,
Case compare generates correct code,
Divide properly takes on signed flag,
Signed right shift sign-extends its argument to prevent loss of sign bits
and uses the NetSignExtend instead of simple padding,
Use the correct target node for reduction NAND,
Properly handle constant arguments of NetESelect

Handle some exressions that were not handled before, include abs()
and POW.
2008-08-17 08:21:24 -07:00
Stephen Williams e8804500b0 Replace an assert in vvp/arith.cc with a detailed message.
... and an assert.
2008-08-16 19:02:09 -07:00
Stephen Williams 66bed241f1 Prevent silent overflow of mantissa
When converting a binary constant to a real value in the vvp code
generator, make sure the mantissa does not overflow. If it does,
panic in some way.
2008-08-16 18:30:07 -07:00
Stephen Williams f8bd8e1bd6 Unary minus and signed right shift need to extend their arguments.
In signed contextx, the right shift and unary minus expressions need
to be sign extended before they operate, otherwise there may be bad
results in the high bits in the greater context.
2008-08-16 17:30:32 -07:00
Stephen Williams d2eba7eefe Modulus value bit width should match input dividend width. 2008-08-16 16:25:56 -07:00
Stephen Williams 5ddf34d39b Signed operands do not make power (**) real. 2008-08-16 15:36:14 -07:00
Martin Whitaker 2c1426a44d Patch to ensure functions are evaluated immediately.
This patch causes a thread that is created to evaluate a function
to be executed immediately. The parent thread is resumed when the
function thread terminates.
2008-08-16 14:42:17 -07:00
Stephen Williams 30e6cfce41 Real valued nets are signed, and pform unary expression have width.
Real valued nets should ne treated as signed no matter what.
Also, PEUnary nary expressions need a useful test_width method.
2008-08-15 22:03:19 -07:00
Stephen Williams 1ae2c0c9e0 Extra diagnostic details in elaboration of continuous assignment. 2008-08-15 21:19:04 -07:00
Cary R 1f5b11246e Correctly pass a concatenation elaboration error.
Because Icarus tries to elaborate as much as it can even after
an error has occurred we need to check for these errors during
elaboration. This patch prevent an undefined identifier from
crashing the compiler.
2008-08-15 17:26:08 -07:00
Cary R d3caa547ba Print an error for automatic tasks or functions.
This patch adds code to recognize and report that automatic
task or functions are not currently supported.
2008-08-15 17:10:59 -07:00
Nick Gasson 026d941734 Avoid printing field widths in $display/$write output
This removes some unwanted artifacts from the output.
2008-08-15 19:43:16 +01:00
Stephen Williams 61b9c5e069 Pad signed expressions in continuous asignments
When the continuous assignment is signed, then sign-extend the r-value
in the few cases where the expression is stubbornly smaller then the
desired width.
2008-08-14 20:38:34 -07:00
Stephen Williams 4b646aca90 Account for signed multiply
When multiply is done in native words, the conversion to words from the
vp_vector4_t vectors must be done signed. This only matters if the
input operands are different sizes (and themselves signed) but will
not hurt even if we want an  unsigned result.
2008-08-14 20:37:04 -07:00
Stephen Williams 50c1533fdd Fix evaluation of logical equality with x bits.
Logical (in)equality needs to look at all the bits of both operands,
and cannot short circuit the test unless defined bits differ. If there
are undefined bits, the equality is undefined at that point, but return
x only if there are not other bits that make the results clearly
unequal.
2008-08-13 22:22:59 -07:00
Nick Gasson a577ee447b Generate process for sequential UDPs 2008-08-13 17:03:03 +01:00
Nick Gasson d7b85c42a0 Split sequential and combinatorial UDPs into separate functions 2008-08-13 11:57:05 +01:00
Stephen Williams 3def0e0dec Fix some expression elaborate vector width problems. 2008-08-12 21:32:21 -07:00
Stephen Williams dc6d3f4afb Fix a spurious non-local net.
During elaboration of continuous assignment that connected the rval
to the lval with a part select forgot to mark the signal it created
as temporary.
2008-08-12 21:31:39 -07:00
Stephen Williams 3d1f363be8 Handle special case of net assigned to net.
When nets are assigned directly to a net, we need to create a driver
to carry the strength. Normally, the implied drive of a continuous
assignment is carried by whatever gate the r-value expression ends
with, but with simble net-to-net assignment, there is no net so we
need to install a BUFZ to carry the assignment.
2008-08-12 21:03:38 -07:00
Nick Gasson dea54df71b Catch possibly NULL return value
This is caused by using a hierarchical reference (which can't
be translated to VHDL). The result of get_decl is NULL since
the signal has been declared in a different VHDL architecture.
Adding the assert is cleaner than having it segfault, for the
moment, until a nicer error message can be added.
2008-08-12 09:47:03 +01:00